We have been designing a simple 32-bit RISC-V CPU using the base instruction set, RV32I (+5 stage pipeline). We also had a presentation in Advanced Logic Design course in Iran University of Science and Technology, about CPU design and simulations based on the open source ISA, RISC-V. If everything looks OK, upload the zip file to JLCPCB order page.Me and my friend, Faraz Ghoreishy have been researching and working on CPU designing and computer architecture for a while. Please put them into a single zip/rar file.Īltium has published a guide on producing those files here: Generate the Drilling layer in Excellon format.įile -> Fabrication Outputs -> NC Drill FilesĢ.

This tool allows you to verify that all layers have been generated correctly and that they are all in positive mode.ġ. Gerber Files are automatically loaded in the Altium cam viewer. Please click the OK to generate the gerber files. When you make sure all configurations are fine. Include the layers that you want to export by marking these, lect “Used On” in Plot Layers, Select “All Off” in Mirror Layers.īe sure to mark “Embedded apertures (RS274X)” If your board are 2-layer, there will be no inner layer(G1,G2,G3.) Please make sure you have the clear outline in mechanical layer.

In the General Setting set the precision to 2:5 (0.01 mill resolution)

Select File -> Fabrication Outputs -> Gerber Files. PCB design files on Altium designer software If you have corrections or find errors, please email support.ġ. Use your judgment and always verify your designs meet our capabilities to prevent design defects that could affect your boards. Note, these files are not exhaustively validated or guaranteed by JLCPCB. JLCPCB-4-Layer-Stackup.zip JLCPCB-6-Layer-Stackup.zip Our Kind customer has provided loadable DRC rule and Stackup files for our multilayer services.

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